Based On The Research Of 0.18 Mu M Cmos Technology Pipelined Adc And Design

ADC which converts the analog signals to digital signals is an interface between analog and digital worlds. Nearly all the signals in the nature are continuous, while the signals which are easy to process, analyses and transmit are discrete. Thus ADCs are needed to convert these signals to digital ones. Therefore, ADC design are the more and more important in today’s electronic technology development process.This paper proposed a10-bits40Msps pipelined ADC based on0.18μm CMOS technology in Cadence Spectre under1.8V power supply,and the circuit structure is implemented by using9levels, of which the1st～8th is1.5bits/level while the9th is2bits/level. Sample-hold circuit, sub-ADC, sub-DAC, bandgap reference, clock generator and digital calibration circuits are the main components of the proposed ADC. To maintain the accuracy of the input signal, the sample-hold circuit which contains folded cascaded and common source2-stage operational amplifier is needed, Miller compensation is between the2stages,80dB gain is achieved. The sub-ADC is of the dynamic comparator structure to meet the need of the main ADC. Bandgap reference is employed to provide a1.2V voltage, within the range of-50℃～100℃, temperature coefficient is10.6ppm/℃, the variation is2mV only. With the aid of digital calibration circuit, error and redundant bits are removed. After simulation, each module circuit accord with this paper request.