Design And Research Of Key Cells Of ADC For GPS Receiver

With the development of GPS receiver in wireless communication system, the high performance analog-to-digital systems are demanded. ADC is the interface between analog signal and digital signal. In the GPS system, the analog signal coming from Mixer is transferred into digital signal, and then sent to Base band. Comparing with other most ADC architecture, the pipelined ADC can achieve high speed and high resolution. Furthermore, the number of comparators will be decreased, so as to the area. Meanwhile, with the development of technology of IC, lower voltage and smaller mix-signal system is more important. In this design, we introduce the unit circuits of pipelined ADC whit 1.5 bit per stage.First, the Matlab-Simulink tool was used in ADC's system level simulation, the model of pipelined ADC is established and proofed, the influence of offset voltage, offset capacitor and gain error to output range of pipelined stages was discussed, the high performance operational amplifier was employed in circuit design and capacitor matching was considered in layout design.Second, the circuit was designed in SMIC 0.18μm mixed CMOS technology and stimulated by Cadence Specter in this paper. The analysis and design of S/H, subADC, MDAC were presented. Finally, the and layout and post simulation are shown in this paper.The flip-flop S/H circuit with the advantages of high gain and wideband of gain-boosting operation amplifier were used to achieve 10-bit, 40MHz specifications required in the paper, the ideal of S/H was employed in the design of MDAC circuit, dynamic comparator was use in the design of sub ADC. The simulation results shown that the circuits meet the required specifications.