The Design On A Low Jitter CMOS Phase Locked Loop

The phase lock technology has one hundred years history and is widely applied in clock generation, frequency synthesis, 3G wireless communications and other areas. The ultra-high-frequency, high-bandwidth, high integration, low power, low price are the main development directions of the phase-locked loop. Phase lock technology plays an irreplaceable role in the electronic age. The modern PLL is applied in many systems, the requirements for the jitter or phase noise continue to increase, especially in the audio and video processing chip, wireless communications chips field.A phase-locked loop is designed in this thesis, which is applied to 24bit Audio Codec chip providing the clock for Sigma Delta ADC. We must make effort to reduce the phase-locked loop's jitter. The application background, classification, types and performance of phase-locked loop are described. After every modules of PLL are analyzed, the Z-domain of phase-locked loop circuit is analyzed to ensure the correctness of the design. The effects of PFD, charge pump, loop filter on the noise and jitter characteristics of PLL loop are in detail taken into account during circuit design. The most important module in the phase-locked loop is the voltage controlled oscillator. The voltage-current converter module and the current frequency conversion module are designed and analyzed, its impact on the PLL jitter is taken into account. During the overall circuit design, effective effects are taken to prevent unreasonable impact jitter of PLL, such as the PFD, the "dead zone" may appear in charge pump design, current mismatch and so on. For the VCO design, the conversion circuits from the current to the voltage, from the frequency to the currents are in detail analyzed, described and simulated. The system performances are simulated and analyzed with HSpice software under different process corners. The whole layout is planned. The symmetrical layout is adopted for the voltage controlled oscillator, the power line, the clock line, the signal line are planned to ensure the function and the performance. The phase-locked loop is designed and fabricated based on TSMC 65nm process technology. The tested results show that the frequency ranges from 6MHz to 96MHz, RMS jitter is less than 50ps, the operating voltage is 3.3V, and the power consumption is less than 2.5mA.