The Theory Research And Circuit Design Of CMOS Integrated Charge-Pump Phase Lock Loop

With the high speed developing of the integrated circuit technology,PLL circuit obtained more and more attention,and it plays an important role in VLSI and SOC system. Because its low power dissipation,no locked phase error in theory,low jitter and wide capture area,CPPLL becomes the mainstream in PLL design nowadays.This thesis beginned from the theory research of PLL,built the linear and non-linear model of loop,contains detailed analyse of dynamic character,track character,capature time,stability problem.A top-down design order is flowed from CPPLL system research to its transistor level design step by step.Finally,it designed a CPPLL worked on 25-58MHz frequency in 3V power and 43-100MHz frequency in 5V power,the phase noise of oscillator is -98.5dBc/Hz@1MHz.The circuit structer chosed a fast precharge PFD,a charge pump without charge share and clock feed through effective,a LPF eliminated voltage ripple,especilally a five stage differential ring oscillator which restrained interfere from power and bulk and got a high linear maglitude-frequency curve.Finally,considering the complexity of mixed IC design,a layout was drew following the commonly principle and specific requirements.The circuit of this paper used Cadence Spectre tool,simulated under CSMC CMOS 0.5μm1P2M library,the layout is finished by Cadence Virtuoso tool.It was proved that the individual part and whole loop achieve the design target.