Analysis And Design Of 14-bit 100-MS/s Pipeliend Analog-to-digital Converter

High speed high resolution Analog-to-Digital converters (ADCs) are the building blocks in consumer electronics and communication systems, for example a 12bit 200Msample/s ADC is needed in wireless infrastructure to process digital signal, and high speed high resolution ADCs are prohibited to export to China due to The Wassenaar Arrangement. Therefore, it is a challenging work to do research on high speed high resolution ADCs. There are several types of high speed high resolution ADCs, such as sub-ranging ADC, Folding ADC and Pipelined ADC, of which the pipelined ADC is the most efficient topology to realize the high speed high resolution analog-to-digital conversion. The pipelined ADC is often used in data acquisistion systems, video processing and some 3G wireless applications. This thesis focuses on the system design of high speed high resolution pipelined ADC, and then the circuit level and layout level design are made after understanding each part of the pipelined ADC system. In the final, low power design is necessary for IC design.There are several non-idealities in pipelined ADC, such as the on-resistance of sampling switch, the finite gain of opamp and finite bandwidth, the offset of comparator, the variation of reference voltages, the capacitor mismatch and the circuit noise. Therefore, we have to consider these non-ideal factors which degrade the performance of pipelined ADC. Through the Matlab modeling of the pipeliend ADC system, we can analyze these non-ideal factors by the output spectrum and know the importance of them in circuit level design. In order to reduce the effect of non-ideal factors, we propose a foreground digital calibration method to calibrate the capacitor mismatch and verify the algorithm in Matlab. Also, the calibration method works effectively. Finally, we choose the 1.5bit per stage as the stage of pipelined ADC considering the trade-off of power and speed. The whole pipelined ADC includes 14 1.5bit stages and a 2bit Flash stage, and the extra two 1.5bit stages are used for digital calibration.The proposed digital calibration method is realized based on digital design flow method, that is to say, we first write the Verilog code using digital software, and synthesize the code to make the circuit for simulation. After simulating the code-based circuit and verify the correctness, the layout of the circuit is realized and the parasitics are extracted for post-layout simulation. If the result does not reach our goal, the process described above should be repeted until the specifications are reached through revising the parameter of digital software tools to finish the design of digital calibration circuitry.A 14-bit 100MS/s prototype pipeliend ADC is implemented in this paper, which is fabricated with TSMC 0.18μm CMOS process. The ADC achieves SNR of 64.1dB and SFDR of 74.3dB with 1MHz input frequency and 40MS/s sampling frequency after digital calibration. With the input frequency reaches 20MHz, the SNR reduces to 53.6dB and SFDR reduces to 64.5dB. The DNL of ADC is +0.47/-0.5LSB and +0.38/-0.36LSB, while the INL of ADC is±12LSB and +2.2/-2.1LSB respectively before and after digital calibration. The whole ADC chip consumes 180mA current at 40MS/s clock frequency, which is 594mW power consumption from 3.3V voltage supply.