Design Of Low-Power High-Speed High-Resolution Pipelined ADC

With the rapid development of integrated circuit technology and computer technology,information processing methods are becoming more and more digital.As a key device connecting the analog system and the digital system,the Analog to Digital Converter(ADC)has been a research hotspot in the field of integrated circuits.Compared with other types of ADCs,pipelined ADCs have become the mainstream architecture for applications in wireless communications and high-definition digital media because they can take into account speed,accuracy,power consumption,and area.Especially in recent years,the emergence of 5G communication technology and ultra-high-definition digital media has pushed the pipeline ADC to develop in the direction of low power consumption,high speed and high accuracy.Moreover,with the rise of digital circuits,more and more pipeline ADCs are often corrected using digital calibration techniques.The digital calibration techniques can correct the error caused by non-ideal factors in the analog circuit,and then improve the overall ADC performance indicators.Based on the 40nm CMOS process,this thesis studies the key circuits of low-power,high-speed,high-precision pipeline ADC and designs a 12bit 250MSps Pipeline ADC.Considering the low power consumption of the Pipeline ADC designed in this paper,the SHA-less Pipeline ADC structure is adopted and the size of the pipeline sub-stages is gradually reduced.In this paper,the working principle and the key circuit module of the SHA-less pipelined ADC is introduced in detail.At the same time,the source of errors in the circuit are analyzed,and the corresponding solutions are also proposed.In addition,this paper also introduces a background digital calibration technology based on pseudo-random noise(PN)injection.This calibration technology can adaptively calibrate the closed-loop gain and effectively improve the accuracy of the ADC.Moreover,the calibration technology is fully integrated on-chip,which can track the changes of the closed-loop gain and has good stability.Finally,the design uses a 12-stage pipeline structure,in which the first 11 stages are all 3bit pipeline sublevels with the same circuit structure,and the last stage is a 3bit flash ADC.The final chip layout size is 1310?m×510?m,where the analog part of the layout area is 950?m×510?m,and the digital part layout area is 360?m×510?m.With sampling frequency 250MHz,input frequency 86MHz,power supply voltage 1.1V,differential input full swing 1.2V,after calibration the simulation results of circuit are that SNDR is 72.15dB and SFDR is 89.85dB.The simulation results of the layout are that SNDR is 72.76dB and the SFDR is 81.31 dB.The total power consumption of the ADC is 150m W,of which the power consumption of the analog part is 140mW,and the power consumption of the digital part is lOmW,and the FOM is 0.18pJ/step.