Clock Network Design By Semi-Custom And Full Custom Mixed Flow

With the fast development of IC (Integrated Circuits), the integrity and frequency of chip is gradually raised, and the requirements of the chip on the clock system are more stringent. This paper focuses on semi-custom and full custom mixed-design system of large scale integrated circuits for high-speed, which is engaged in reseach on problems existing in clock network design, and corresponding suggestions are proposed to solve the problems.In general, clock network design has some problems, including clock generation, clock skew, clock drive capability, how to use the time borrowing and useful skew. In addition, it's necessary to take such problems in semi-custom designs as the clock division frequency, multi-clock domain synchronization, as well as clock linked up in the mixed design into consideration. In this paper, it intends to solve these issues through theoretical analysis and engineering applicaton, and finally shows some complete clock network solutions to the problems in semi-custom and full custom mixed design, which is proved to be reasonable.The main contents described in this thesis are summarized as follows:1. It implements the CAM internal clock network with full custom. The requirements of clock skew are so high that it tries to reduce clock skew in the clock tree design. For the purpose of solving the clock skew problems, the structure of Muller C elements have put forward in this thesis.2. In semi-custom design, when multiple clocks frequency are needed to be divided in the system, but phase-locked loop can not meet the demand of the design, It has to be respectively implemented by designer. In such a circumstance, this paper gives an algorithm of frequency division for arbitrary number which can well achieve frequency division for any number in the digital integrated circuit design.3. It implements a design of verification chip of the CAM combined with the test module based on 65nm technology, optimizes timing, exports GDSII file, and passed the DRC, ERC, and LVS, etc. Experimental results show that the maximum value of clock skew is 40.4ps, and useful skew is controlled within 200ps, when the demand for clock frequency is 1.5GHz. The CAM's clock network has been designed with custom design methord, thus, the reserved maximum rise delay is 132ps and the minimum rise delay is 62.3ps in the clock tree synthesis of the CAM and the test module mixed design.The results mentioned above provide us with a number of possible ways to solve the problems existing in the design of the clock network, and some valuable suggestions are presented for the clock network of semi-custom and full custom mixed-design.