Semi-custom Physical Design Methodology Research Based On Owned Embedded System CPU

As technology develops, IC design has stepped into the nanometer scale SOC era. The huge circuit scale along with all kinds of novel process technology issues, bring new challenges to the IC physical design methodology. How to improve physical design approaches and flow is greatly significant in industrial and commercial field for decreasing the product development period as well as ensuring and promoting the integration performance of a chip.A novel semi-custom physical design methodology is proposed based on an embedded system CK series CPU which owns the complete intellectual property rights. This approach merges the transistor level adjustment and optimization into the entire IC physical design flow according to a novel reconfigurable standard cell frame. Utilizing a network graph partition and simplification algorithm, the method extracts the objective circuit available for tuning which is consequently used for implementing a trade-off optimization between cell delay and net delay by taking the net delay variation during the transistor adjustment procedure into account. In comparison with the traditional methodologies, this method realizes the circuit performance optimization in addition to decreasing the complexity and difficulty of transistor tuning on a chip and meanwhile maintains the design convergence and iterations.Based on the reconfigurable perspective, a novel delay controllable clock buffer (DCCB) is proposed for clock period optimization via a clock tree adjustment algorithm which generates useful clock skew according to DCCB reconfiguration and direct layout modification. Experiments indicated that this approach improved the clock period by approximate 10%-17% higher than the traditional methodologies.Finally, the dissertation discusses the primary research on SRAM timing library generation and presents the SRAM timing library extraction approaches concretely.