Data Acquisition And Pretreament Interface Design Of JPEG Video Decoding Chip Based On FPGA

With the continuous development of multimedia and computer technology, multimedia information such as sound, picture, video are very common in people's daily life. JPEG image compression techniques make it is convenient to store and transfer this information. At the same time, kinds of special decoding chips appeared in the market. Compared with the traditional software coding method, the special decoding chips have higher execution efficiency.But most of them only have one founction, coding or decoding, and some of them only support one or two video format.And most of them are designed by foreign companies who don't want to publicize their design methodology. So we put forward an idea that implementing the codec and transfer of dynamic video in a single chip and both encoding and decoding can work at the same time. And it is very meaningful for us to do this try.The work which is going to done in this paper is to complete the design of the interface that is used for data acquisition and pretreatment. It is one part of the whole project. Paper introduces the knowledge of the JPEG standard and EDA technical at the beginning, and then make a discussion about FPGA, including the FPGA working principle and the development process of it. We make the function of the interface clear and give out the framework of the interface on the base of the demand analysis. After that,we use Verilog HDL language to realize the design of the interface. Finally, we complete the functional simulation by using Modelsim and FPGA hardware verification by using the development board.In this paper, we put forward a kind of data pretreatment method, which is realized the division of the Minimum Coded Unit that is mentioned in JPEG standard.And it also brings a positive reference to other similar design works.