Fpga-based Jpeg Codec Chip Design

In recent years, with the fast development of electronic technology and image compression technology, real-time image processing is widely used in the field of multimedia, HDTV and image communication. At the same time, the ICs of image compression/ decompression become the core of multimedia techniques, while the research about the algorithm used to design ICs is the new key-point in information industry.This paper presents an IC design of JPEG image compression/decompression based on FPGA. Through improving algorithms and optimizing structures, with conditions of efficiently using of hardware resource, the utility of the parallel algorithm is exploited more efficiently. In the design of JPEG coder, JEONG algorithm on DCT transform is improved, the problem of time parallel is resolved with pipeline optimization algorithm, and the speed of DCT/IDCT module is accelerated. According to the orderliness of Huffman coding table, the operation of Huffman coding can be finished using less store unit based on parallel LUT (Look up Table). At the same time, the speed of coding is improved. In the design of JPEG decoder, according to the characteristics of Huffman code and JPEG standard, a clustering structure of Huffman code is designed. Based on the structure, a design method for LUT of Huffman code and address coding is given, then the designs of a new algorithm about fast Huffman decoding and the hardware module based on the algorithm are worked out.The full design and each module are synthesized in logic, then are simulated in function and timing on QUARTUS II EDA tool-desk of ALTERA Corp. The result of synthesis and simulation indicate that the IC design of JPEG image compression/decompression based on FPGA can give a better performance on speed and resource using with less hardware resource and a higher frequency, and can meet the requirement of real-time application of JPEG image processing.Based on the design, hardware simulation can be done in the next step, and then the source code can be downloaded into FPGA. As a separated JPEG device or IP module, the design can be applied to low-cost system of JPEG compression/ decompression, such as cell phone, vision phone and conference TV.