The Development For The Low-Cost Image Acquisition And Processing System Based On FPGA

With the rapid development of digital multi-media techniques,image acquisition and processing are applied in more and more fields.CPLD and FPGA being large-styled and programmable logic device(PLD) are nowadays two kinds of programmable application specific integrated circuit(ASIC) that is being used most extensively. Electronic engineer can get the ASIC they need by using CPLD and FPGA in their offices or laboratories, thus the time of products' appearing on the market is shortened consumedly and the development cost is lower.We adopt a chip design approach based on larges cale FPGA that conforming to the trend of digital circuit design and therefore the design time is shortened. We use two boards architecture to reduce the cost and make it easy to debugging.The dissertation includes hardware design and FPGA logic design.FPGA logic design is to design function module using Verilog hardware programming language. The chapter of the software in this dissertation introduces the implementation of each module.In hardware design, the components of the function circuit and the design method of the two boards architecture are introduced. Also we have done some analysis to the various aspects of the Circuit performance.The evaluation of the image acquisition system shows that its performance reaches the requirements of the system, and it can work reliably with low power consumption.