Jpeg Encoding Algorithm Based On Fpga-optimized Design And Hardware Realization

In day-to-day life, a large number of digital information is stored, processed and transmitted every day. The problem solved by image compression is to minimize the amount of data required by digital image. JPEG still image compression algorithm(ISO/IEC 10918-1),because of the fine compression characteristic for the continuous tones,multi-level gray-scale image,has been widely used and have become one of image compression standard in multi-media communications.This thesis based on FPGA(Field Programmable Gate Array)designed and realized JPEG image encoder. On the basis of briefly introducing JPEG standards and FPGA design process, all the major modules the JPEG encoder was studied deeply and designed the overall structure of the JPEG encoder. In the JPEG image encoder, the consumption time of two-dimensional DCT unit in the entire coding algorithm is about 70% of total coding time, so to increase the clock speed of 2D-DCT unit is very necessary. this thesis used the improved distributed structure to implement 2D-DCT transformation, effectively reduced computing time of the 2D-DCT unit. On the basis of careful analysis to the principle of quantization and ZigZag scanner unit, ZigZag will be integrated into the quantizer, which saves the time of quantization and ZigZag scanning. Using the Verilog HDL designed and implemented JPEG encoder of basic mode and gives the simulation resultsof the main modules of JPEG encoder.The design and implementation of the JPEG encoder provided a exploring attempt on the hardware implementation of complex image encoder based FPGA and a positive reference on the other image coding system IP core design and their FPGA implementation.