JPEG Encoding Algorithm Optimization And Implementation Based On FPGA

With the development of multimedia technology, the image has increasing number of applications, and image processing technology is very important to image information storage and transmission. In image compression techniques, still image compression standard JPEG, have good compression characteristics, therefore, has a very wide range of applications.With advances in FPGA technology, the function is getting stronger, continue to reduce costs, so it is possible to implement complex systems on FPGA platform. Research and implementation of image compression system, has great application prospect, the dedicated image processing chip design is a worldwide research hot spot in recent years. So It is very significant to realize JPEG encoder on FPGA platform.The Verilog hardware description language is used to design and realize JPEG encoder in this article, and take full advantage of rich resources and the flexibility of FPGA in this design. According to the coding process, JPEG encoder is divided into several modules.Whererin the two-dimensional discrete cosine transform using the row-column decomposition method, converted to two one-dimensional discrete cosine transform. And the one-dimensional discrete cosine transform is realize with a modified Loeffler fast algorithm. Largely reduce the complexity of the hardware implementation, improve the processing speed of two-dimensional discrete cosine transform. Quantization is implemented by multiplication instead of division, reduce the impact of division of operation speed. Huffman coding implementation uses a parallel look-up table manner, increase the speed of the encoding. The pipeline technology is widely used in the system design, improve the processing speed of the system by optimizing.And the entire design and every module has carried on comprehensive implementation and functional and timing simulation in Quartus117.2platform. Synthesis and simulation results show that the design of JPEG encoder, use fewer FPGA logic resources, realize higher work frequency, both in terms of hard cnsumption and work speed gets some improvement. And simulation in MTALAB7.0platform, Quartus Ⅱ and MATLAB simulation results were compared and found the error is small.Finally, using real pictures as a test input, the compressed JPEG images can be displayed correctly, and image compression effect is good. This design is correct implementation of the JPEG encoder functions, can meet the requirements of the actual JPEG image compression coding.This design not only can be used as a separate JPEG encoder, can also serve as IP core used in other systems, but also can be further implemented as a programmable on-chip system (SOPC). JPEG encoder design other image codec system design and FPGA platform to achieve a positive reference image compression chip also has certain reference value.