Design And Development Of The JPEG Compress System Based On FPGA

With the rapid development of digital multi-media techniques, image acquisition and processing are applied in more and more fields. Being large-styled and programmable logic device(PLD), CPLD and FPGA are nowadays two kinds of programmable application specific integrated circuit(ASIC) that is being used most extensively.Electronic engineer can get the ASIC they need by using CPLD and FPGA in their offices or laboratories, thus the time of products appearing on the market is shortened consumedly and the development cost is lower. We adopt a chip design approach based on large scale FPGA that conforming to the trend of digital circuit design and therefore the design time is shortened. We use two boards architecture to reduce the cost and make it easy to debugging.The dissertation includes hardware design and FPGA logic design. FPGA logic design is to design function module and write Testbench under the use of Verilog hardware programming language. The chapter of the software in this dissertation introduces the implementation of each module and through the Testbench the correctness of the functions of each module is verified. The hardware circuit design is mainly about the drawing of video decoding circuitry. With the Testbench and timing constraints report, a detailed and specific analysis of the performance of overall system can be made.In this paper, the structures through the video decoding circuit, I2C bus control module and interface module preparation, video image capture, video storage, video images of the JPEG compression, and UART modules completed a total of six parts of the whole system, and the preparation of each module The test platform to verify the correctness of each module's functionality.The evaluation of the image acquisition system shows that its performance reaches the requirements of the system, and it can work reliably with low power consumption.