Jpeg Decoding Algorithm In The Fpga-based Research And Realization

JPEG has been widely used and become one of the international standards for its excellent performance on compressing still image among multimedia communication technologies. On the basis of briefly introducing JPEG standard and FPGA design process, the design principle of the overall decoding structure is proposed. Then, the thesis gives design details of all the major modules of the JPEG decoder which is implemented using Verilog HDL also with the simulation waveforms and the implementing results after the JPEG decoding algorithm was studied deeply. In the JPEG decoder design, it is necessary to increase the speed of two-dimensional IDCT (Inverse Discrete Cosine Transform) module because it consumes a significant portion of the total time in the decoding process. This thesis uses the improved means of ranks decomposition to implement the 2D-IDCT module, which effectively reduces computing time. The inverse Zig-Zag scanning module is integrated into the inverse quantizer, which saves the time of anti-quantization and inverse Zig-Zag scanning. According to the characteristics of Huffman table and JPEG standard, parallel algorithm for entropy decoding is proposed to achieve a fast Huffman decoding.The design and realization action of the JPEG decoder provides an exploring attempt to implement complex image encoders based on FPGA and a positive reference to the systems IP core design and their FPGA realization. of the other image decoding.