Still Image Compression Coding Standard Jpeg Mode And Fpga Implementation

The thesis discussed about how to implement the JPEG Baseline Mode Compressed Encoder on the device of SPARTANⅡ. The system was designed by the Verilog Language. According to the FPGA design flow of the XILINX corp, the system was synthesised, implemented and verificationed by the integrated tools Foundation 4.1.First, the thesis introduced the JPEG Baseline Mode Encoding Standard. Then it introduced the master plan, including the architecture of the system, the module dividing, the design method and the coding style. After that, the thesis gived out the detail of each module also with the testing datas, the implementing results and the timing simulation oscillograms. At last the Leina image was used to test the whole system, the result datas we got could be identified by the software ACDSee.The thesis gived out the resolution way on FPGA device of the main algorithm of JPEG, such as the DCT transform, the Huffman encoding and the quantization. The thesis also tried to design a interface to exchange datas with slow-speed peripherals.While designing the system, we spent a lot of time in considering how to divide and define each module and how to coordinate and interconnect these modules. We followed the top-down method to design. First defined the top module, then divided the top module to several independent small units. As for the interconnection of each module, we defined the interface signal to communicate between them, and the internal timing of the module was control1ed by states machine. When we construct the logic, we pay much attention to hardware resource spending and concurrent excution of the Verilog Language to make the design close to the hardware work way, so we could get a high speed with a low hardware spending to satisfy the demand of the cost, performance and practicability. It also gived out some reference for the future SOC.