Design of current-mode folding and interpolating analog-to-digital converters

Folding and interpolating converters use continuous-time analog circuits to create “folded” signals that reduce the dynamic range of the input, thus reducing the number of comparators required for a flash ADC type conversion in a single clock cycle and leading to a reduction in component cost, area and power.; Folding amplifiers used in folding-and-interpolating analog-to-digital converters are designed using a CMOS or bipolar differential stage. The non-linearity inherent in the transfer function of this stage yields a corresponding nonideality in the transfer function of the folding amplifier which in turn causes nonlinearity in the folding-and-interpolating analog-to-digital converter. To compensate for the folding amplifier non-linearities, four or eight folding amplifiers are used in the analog-to-digital converter design. This thesis describes the design of folding-and-interpolating analog-to-digital converters including the functionality and design constraints for each block. The design of a folding-and-interpolating analog-to-digital converter using a current-mode highly linear current-mode folding amplifier in a BiCMOS process is described. The design uses a 100MHz clock and has 8-bits of resolution. Only two folding amplifiers are used in this design, demonstrating the benefit of using a linearized stage in the folding amplifier.; A behavioral model has been developed as a tool to analyze the effect of nonidealities on the performance of folding-and-interpolating analog-to-digital converters. It can also be used to determine the specifications of each circuit block in the analog-to-digital converter for optimal system performance.; Typically the resolution of a folding-and-interpolating analog-to-digital converter will drop sharply as the input frequency approaches the Nyquist rate, due to bandwidth limitations of the circuit blocks that lead to signal-slope dependent errors. A sample-and-hold circuit can be added at the input to maintain high performance with increase in input signal frequency. Design techniques for sample-and-hold circuits with high speed and low charge feedthrough are discussed in the thesis.