Ultra-high-speed Adc Clock Stability And Coding Circuit Design

The Analog-to-Digital Converter (ADC) is the main unit between Analog signals and Digital signal. And the digital signal system widely used makes ADC has been more attention, the requirement of the ADC is also increasing in the development. But when the sampling rate and the resolution of ADCs become higher and higher, the effects of clock jitter aperture time uncertainty will cause the sampling offset more and more seriously, resulting in lower signal to noise ratio (SNR) of sample and hold (S/H) circuit, which greatly limits the overall ADC performance improvement.This thesis starts at the study of a Phase-Locked Loop (PLL) applied to the clock system, Comparator and Error Correction of a 8Bit 1.6GSPS ultra high speed time-interleaved folding and interpolating ADC, and the deep analysis of the low jitter single output frequency PLL, High Speed Comparator and Error Correction are unfolded from basic principles, system level design, transistor circuits design and layouts design.The relationship between VCO lock time and PLL system parameters is researched. According to PLL linear model by S domain analysis, deriving that the open loop transfer function, determine the PLL in the main parameters of each module. Some module unit circuits, including PFD, CP, VCO, Divider, Comparator and Error correction are designed based on 0.35μm CMOS mixed-signal process. A charge pump circuit of reducing charge sharing has been developed, the circuit decreased charging and discharging current mismatch. the VCO can inhibit the power noise and substrate noise by combination of current-mode unit and two-to-one circuit, and the PFD using dynamic D flip-flop and exception logic eliminate the PFD device"dead zone"phenomenon.Moreover, the simulation results of the whole clock stability circuit show that the PLL lock time is about 2.2μs at the 3.3V supply voltage, 25℃and the TT process corner. when the PLL is locked in, the controlling voltage of VCO has little ripple, stable at 1.895V, The output frequency range of VCO is 35MHz~1.3GHz, and the linearity of VCO is good with the output frequency of 400MHz. The power of the whole circuit is 32.68mW at 3.3V power supply. In addition, the phase noise of the whole clock stability circuit is -126.85dBc/Hz@1MHz. The Comparator simulation results show that the rise time is 0.2ns, and the fall time is 0.25ns. Also, the PLL can operate well under different process corners.