The Design Of Clock Source Based On Three-order Phase-locked Loop Frequency Synthesis Technology

With the rapid development of modern testing technology and digital communication technology,various new types of electronic equipment and communication system frequency synthesizing technology have put forward higher and higher requirements.It is necessary to input high-speed,high-precision,low-jitter,low-frequency bias clock signals to complete the transmission,reception,and data storage of signals in the fields of radar,electronic countermeasures,navigation,aerospace,deep space exploration,and wireless communications,and combined with other test equipment to verify the correctness of signal processing and the satisfaction of technical indicators.The clock source is an important universal test device for this task.Therefore,it is of great significance to study and design a frequency-adjustable,high-precision,high-reliability,and high-stability clock source.This paper mainly studies and designs a clock source based on the third-order phase-locked loop frequency synthesis technology,and proposes the overall design scheme of the system based on the phase-locked loop technology.Firstly,the principle of the phase-locked loop and its various components are described,and the technical indicators of the clock source design are proposed.Secondly,the high frequency resolution and low phase noise in the requirement are analyzed,and the corresponding solutions are put forward.Then the hardware circuit design was carried out according to the requirements of the indicator,including two-stage fractional-frequency phase-locked loop,phase-locked loop filter,synchronous frequency divider,USB interface circuit and output interface.Finally,the output frequency and phase noise of the designed clock source system are tested.Through the analysis and comparison of the test results,the correctness and feasibility of the system are verified and the technical specifications of the design are achieved.