| Clock signals are needed in many integrated circuits,such as the multi-phase clock signal designed in this paper for time-digital converters.For high-precision multi-phase clock circuit,a small jitter may cause confusion between phases,and then disturb the timing of subsequent circuits,so the requirements for the clock signal quality are more stringent.The PLL offers the local oscillator clock signal to the system,so a PLL with high spur and high noise performance is indispensable.The sub-sampling PLL designed in this paper can avoid the reduction of spur performance in charge pump PLL caused by unexpected factors such as electrical loss and distribution.Moreover,when the loop is locked,only the core loop works and does not have frequency divider,so the in-band noise dominated by the charge pump will not be amplified by the square of the divider ratio.By using virtual sampler,the capacitor load of VCO is kept constant,the control voltage ripple of PLL is reduced,the output frequency of VCO is stable,and the reference spur of sub-sampling PLL is reduced.Since the sub-sampling PLL itself has the characteristics of low in-band noise,a large loop bandwidth can be selected to suppress the out-of-band noise dominated by VCO,and a large loop bandwidth can also accelerate the locking time of the PLL.The improved tunable narrow dead zone generator can adjust the dead-zone time and the locking time of the sub-sampling PLL can be accelerated by reducing the dead-zone time.The main contents of this paper include:1.This paper states the specific research background of PLL and development situation at home and abroad,and introduces the theory of PLL.Each module and its linear model of charge pump PLL are studied in detail,then study the charge pump PLL noise model,and analyzes the characteristics of the loop.2.The overall structure and working principle of the sub-sampling PLL are analyzed.The spur performance and noise model of the sub-sampling PLL are analyzed in detail,the linear function of each module element is derived and the transfer function of the sub-sampling PLL is obtained.According to the design index,the loop parameters of the sub-sampling PLL are calculated preliminarily,and then the stability of the sub-sampling PLL is analyzed by using MATLAB program.3.Based on 110 nm CMOS process,the sub-sampling PLL and multi-phase clock generator circuit are designed according to the design criteria.The related modules of the core loop circuit and frequency-locked loop circuit are first designed.The design idea and process of each module circuit are described in detail,so as to complete the design of the low noise low spur sub-sampling PLL,after that,the simulation analysis is carried out,the locking time of sub-sampling PLL and spur performance are optimized through a series of technology.Through the principle of injection locking,the output of 8-channel 16-phase clock signal is realized,and the design of the whole clock generator circuit is completed,the simulation analysis is carried out.4.Some rules and key points of simulation layout design are represented.The layout arranged problems of each module are analyzed.The layout and wiring are reasonably arranged and the layout design of sub-sampling PLL and clock generator circuit is completed.After that,the simulation analysis is carried out.In this design,110 nm CMOS process is adopted,and the voltage supply is 1.2 V,The simulation results reveal that the tuning gain of the ring oscillator is 1.06 GHz/V,the output frequency range is 541?966 MHz,and the phase noise is 103.5 dBc/Hz@1MHz.The sub-sampling PLL can be locked at 2.84 ?s,the reference spur is-71.25 dBc,and the in-band phase noise is-115.2 dBc/Hz@200 kHz.The power consumption is 13.2 mW,and the area is about 1.2 mm × 0.3 mm.The clock generator circuit can output 8-channel 16-phase clock signals with an interval of 104 ps between adjacent clocks.The maximum deviation between adjacent clock output intervals of the whole clock circuit is less than 1%,and the total power consumption is 96 mW. |
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