Speed ​​clock And Data Recovery System

Recently, serial transceiver develops rapidly with the increasing data speed requirement. The CDR(clock data recovery) is most critical circuits in transceiver, and we will discuss the CDR in this thesis. The CDR using in this thesis is base on semi-digital dual loop CDR architecture. The theory analyze is done firstly, then the chip is designed to verify with the theory analyze. The features of first order and second order CDR will be discussed in detail. Two chips are designed. One uses the first order CDR for 4. 8Gb/s serial transceiver. Another chip uses the second order CDR for 6Gb/s serial transceiver. The measurement result of chips is consistent with the theory analyze. A new circuit is used for fast-lock, CDR will be acquired fast lock correctly with this circuit. A novel architecture is used in the second order CDR for decreasing the loop delay to improve the performance of CDR. Those chips meet the requirement of high performance and low power. Chips have been in mass production status.