Research On High Speed Serial Data Acuisition And Recovery Technology Based On FPGA

With the rapid development of high-speed serial communication system,it is very important to receive and recover the data correctly and efficiently.The oversampling clock data recovery circuit has the characteristics of simple structure and low power consumption.Therefore,with the reduction of the process size,oversampling clock data recovery circuit with respect to other clock data recovery circuit structure(such as the widely used PLL based structure)has gradually shown two advantages:(1)The oversampling clock data recovery circuit has no clock phase feedback loop,so that its phase locking speed is high.(2)The oversampling clock data recovery circuit has a large number of digital units,so it has the advantages of small size,low cost and easy to transplant.These advantages make the oversampling clock data recovery circuit in the field of high speed and low power applications gradually favored by designers.In this paper,the architecture and key modules based on Xilinx 7 series FPGA platform of oversampling clock data recovery circuit are studied and analyzed,and a high speed serial data acquisition and recovery system is designed for 1Gbps LVDS signal.According to the principle of the traditional oversampling clock data recovery circuit,this paper puts forward the design of the algorithm,including oversampling algorithm,edge detection algorithm and data recovery algorithm.In this paper,the basic structure of all kinds of clock data recovery circuit is analyzed,including feedback phase tracking CDR,oversampling CDR and burst mode CDR.Based on the analysis of the circuit structure and the practical application platform,the oversampling clock data recovery circuit is selected as the basic architecture of the system.After the completion of the algorithm design,the paper focuses on how to use the Xilinx 7 series FPGA to achieve the above algorithm.The high speed serial data acquisition and recovery system designed in this paper is based on the 1Gbps high speed serial data.Due to the limitation of the hardware platform,the traditional over sampling structure can not be implemented on the FPGA platform.Therefore,according to the design of the algorithm,the sampling clock and the input data are copied and phase shifted.Two channels with phase difference are used to sample the replicated data,and the data recovery module is designed to track the jitter of the system in real time.According to the design of this paper,the sampling clock frequency can only be realized by 500 MHz,which can be used to sample the input signal of 1Gbps.So the requirement of the hardware platform is greatly reduced.Finally,in the ISE development platform,the HDL cdoe is synthesized to get the RTL structure of the system.The whole system is simulated by using several types of input signals.After the simulation,the bit stream file downloaded to FPGA is generated by mapping,layout,pin assignment and other work.Finally,the function of the system is verified by the actual signal acquisition and recovery.The simulation and test results show that the system can achieve the function of data acquisition and recovery when the input signal rate reaches 1Gbps,and the 131072 bit data are error free.