Research And Design Of 5.3GHz Low Phasenoise VCO And PLL

The voltage controlled oscillator and phase-locked loop circuit are important circuit modules in the satellite communication link,and are an important guarantee for the successful transmission and reception of information in satellite communication.The design of stable,low phase noise,low jitter voltage controlled oscillator and phase-locked loop circuit can effectively improve the communication quality and product competitiveness of satellite communication chips.This paper firstly analyzes the basic principles and technical specifications of voltage-controlled oscillators and phase-locked loop circuits,and points out the key module circuits that affect the performance of phase-locked loops and points out the key technologies that need to be paid attention to during the design of phase-locked loops.Then,the Colpitts voltage-controlled oscillator circuit with low phase noise is designed and the oscillator circuit is simulated and verified.Secondly,a divide by four circuit and a low-jitter multi-modulus frequency divider circuit are designed based on the CML structure.Furthermore,the crystal oscillator circuit,the phase frequency detector and the charge pump circuit are designed to overcome the dead zone effect of the PFD and the non-ideal effects of the CP circuit.Finally,the layout design of each key module circuit is carried out,and the phase-locked loop module is integrated into the satellite digital broadcast receiving chip for MPW test verification,and the preliminary test results are given.The main results of this paper are reflected in:(1)Based on the Colpitts structure voltage-controlled oscillator,and the buffer amplifier circuit and the oscillation circuit are designed and stacked to realize current multiplexing.The Colpitts voltage-controlled oscillator circuit with low phase noise is designed to provide orthogonal local oscillator signals for the satellite digital broadcast receiving chip.(2)The CML structure divide-by-four schematic is designed using the spurious suppression technique,and the 2/3 frequency divider schematic is improved.The low-jitter multi-mode frequency divider circuit is designed by the cascading of 2/3 frequency divider.(3)The crystal oscillator circuit is designed to provide th e reference clock signal for the phase-locked loop.The PFD circuit without dead zone is designed.The charge pump circuit is designed to improve the matching of the charge and discharge current of the CP circuit and reduce the spur of the VCO.In addition,through the layout design and MPW chip verification of the voltage controlled oscillator and phase-locked loop circuit,the feasibility of the designed voltage-controlled oscillator and phase-locked loop module is proved.The performance of the phase-locked loop is also good.