Fpga Chip Testing Methods Research

Field Programmable Gate Arrays(FPGAs) are programmable platforms for lots of applications.FPGA test is a difficult unsolved problem due to the complexity of FPGA architecture.To design a test procedure for a FPGA architecture costs long time and a lot of money. Although many researchers have done so much work in this area,this process is not fully automated yet in the FPGA industry.This paper proposes a novel traverse algorithm targeted for the detection of Programmable Interconnect Points(PIP) open faults.The proposed algorithm has been developed based on the router algorithms of FPGA.It first builds the test resource graph,and assigns the input and output ports.The test configuration files will cover resource nodes as many as possible.The algorithm was tested using FPGA-1.All 160 files achieve 99.59%coverage of PIPs in FPGA-1.From the practical point of view,testing open faults is not enough. This thesis presents an automatic test-configuration-generation algorithm for application-independent SRAM-based FPGA switch blocks.By constructing the routing resource graph,this algorithm assigns a dynamic weight of each edge by the direction of nets and run the modified Kruskal algorithm to obtain the minimum numbers of test configurations.For different FPGA routing architectures,few test configurations are required to cover PIP faults of stuck-open, stuck-closed,and line segment faults of open and bridging.The proposed algorithm is fast and architecture-independent.