Research On Sram Test Technology For FPGA

A Field Programmable Gate Array(FPGA)is a reconfigurable integrated circuit which is a hardware platform for implementation of any digital design. Recently FPGA testing technology achieved very high developing speed in the industry. Due to the reconfigurability of FPGAs, diffirent designs can be mapped into the same device. Manufacture testing of FPGAs requires a muber of test configurations and test vectors in order to guarantee the functionality of the chip for all possible configurations.This dissertation researched the technology of testing FPGAs. Based on a detailed analysis of the architechture of FPGAs, this dissertation gives out a technology to test FPGAs and a testing platform for the testing of actual FPGA devices.Researched the methods to test Configrable Logic Block(CLB) and its sub-blocks. Based on a"Divide and Conquer"methodology, the CLB resources are divided into three basic blocks: Logic Units, Carry Logic Module(CLM) and LUT's (Look Up Tables) RAM-mode. The testing configurations are implemented based on a two-dimensional array structure for logic blocks.Researched the methods to test Interconect Resource(IR) witch include interconnect lines and NMOS switchs. Based on specific fault models, the testing configurations are implemented by handcraft following the popular testing method of data-bus. Only four testing configurations are used to completely test interconnect resources. We also developed a platform for online hardware software co-testing of FPGA devices. The platform is based on a hardware modeling system connected to common EDA simulation tools. Test vectors are generated by software and applied to the devices under test. The platform achieved very high testing speed and flexibility.The result of this research provides great grarantee to the design of FPGA devices, and gives a big contribution to the FPGA tesing research. This research helped the problem of foreign companies'monopolization on the technoly of testing FPGAs.