.14-bit 100 Mb / Sec Sampling Pipelined Adc

Radio architecture design has changed with developments in digital signal processing and data conversion,allowing the commercialization of the wideband software programmable radio transceivers.Further,these developments allow the architectures whose frequency channels and protocols can be defined by software.This is especially relevant for wireless base-stations,where it offers significant benefits:reducing the cost,size,complexity,and power consumption of a base-station.More important,it can support a variety of modulation schemes and protocols.These high performance transceivers place very stringent demands on the analog-to-digital converter(ADC).The pipelined ADC architecture,based on the switched capacitor(SC) technique,has most successfully covered the widely separated resolution and sample rate requirements of these receiver architectures.This thesis focuses on the design of a high speed,high resolution and high spurious free dynamic range(SFDR) pipelined ADC for cellular base station applications.This ADC is with 14-bit resolution and 100MS/s conversion rate.At the beginning of the thesis,the application,state of art and trend of ADC is introduced.Then from the view of system,the architectures for realizing high speed high resolution pipelined ADCs are discussed,the non-ideal factors are analyzed and a digital background calibration method is proposed to mitigate the non-linearity in conversion.From the view of circuit,detailed analysis and design flow of the key blocks are presented.These blocks consist of improved bootstrap sample switch,miller compensated gain-boosted two-stage amplifier,fast low kick-back comparator and low-jitter clock circuit etc.At the last of the thesis layout techniques,test setup and measured results are introduced.The proposed ADC is fabricated in SMIC 0.18μm one poly six metal CMOS Mixed-Signal process occupying 7.16 mm~2 die area and consuming 220mW(excluding output driver) at 1.8V power supply.Measurements shows that,after calibration,the ADC achieves 14-bit linearity with +0.18/-0.18LSB DNL and +1.1/-0.6LSB INL.At 100 MS/s, the ADC acheives 75.1dB SFDR and 66.1dB SNDR for an input signal of 8.1 MHz,and maintains 74.5 dB SFDR and 61.2 dB SNDR for an input signal of 502.8 MHz.