.32-bit Microprocessor Digital Cmos Delay The Phase-locked Loop Design

With the development of IC technology, the main frequency of micro processor has grown up year by year. Nowadays, most of the large companies like Intel has produced processors with frequency of more than 3GHz. Besides most of the common processors have already worked at the frequency of more than several hundred MHz. The motherboard can hardly provide a clock with the frequency of more than 200MHz because of PCB's limits.Technology lock-in make this easy, but there are many new problems. With the need of low power, fast lock-in time, lock jitter and reconfiguration design, we have to bring something new to meet demands. The common technology lock-in always use a lot of analog circuits, and this makes the design process much more complex and hard to realize. What's more, power consumption and serious clock jitter make us troubled. Because of the ADDLL, people have a deeper understanding to technology lock-in.How to get a satisfied control precision is always a problem in the design of ADDLL. The key technique to improve the control precision is the design of digital controlled delay-line. In this paper, the author implements a new kind of delay-line which has a high control precision and a good control linearity. The author make some improve to the new structure. In this paper the author gives a simple formula to estimate the delay and standardize the design procedure. This makes the design of ADDLL much more simple.Base on the DLL has more advantage than the PLL, and the ADDLL is fabricated in 0.18um CMOS process by custom design. The proposed chip has a reference clock of 80~133MHz. With the comparison of the equivalent design, the lower power consumption, faster lock-in time and a smaller die area.