Research And Implementation Of A DLL Based High Frequency Clock Generator

With the develop of IC technology, the main frequency of microprocessor has grown up year by year. Nowadays, Intel has produced processors with frequency of more than 3GHz. Besides, most of the common processors have already worked at the frequency of more than several hundred MHz. As the mainboard can hardly provide a clock with the frequency of more than 200MHz, we need a high frequency clock generator (HFCG) inside the chip.The common used HFCG are usually designed on the basis of phase locked loop(PLL) or delay locked loop(DLL). Although with high stability, these systems have to use a lot of analog circuits, and this makes the design process much more complex and hard to realize. Also , with all the disadvantages ,these systems can not well meet the need of low power, fast lock-in time and reconfiguration design.The all digital HFCG(ADHFCG) uses digital elements to take the place of the analog circuits in PLL and DLL. So, in contrast with the common used HFCG, these systems have much simple design process and they can well meet the need of low power, fast lock-in time and reconfiguration design. This kind of HDCG has abstracted more and more attention recently.How to get a satisfied control precision is always a problem in the design of ADHFCG. The key technique to improve the control precision is the design of digital controlled delay element(DCDE). In this paper, the author implements a new kind of DCDE which has a high control precision and a good control linearity. With the common used DCDEs the designer has to make a lot of simulations to get the actual delay. It is complex and time consuming. In this paper the author gives a simple formula to estimate the delay and standardize the design procedure. This makes the design of DCDE much more simple.A difficulty of DLL based HDCG is the realization of the frequency multiplying(FM) circuit. How to get a high multiply factor and make the circuit work only at the rising edge(or the falling edge)of the reference clock is a problem. The used FM, nowadays, only has a multiply factor of less than 5. In this paper the author implement a new FM circuit. This circuit has a multiply factor of more than 10 and only works at the rising edge of the reference clock.At the end of the paper, the author implement a DLL based HFCG with the proposed DCDE and the proposed FM, and the HFCG is fabricated in 0.18um CMOS process by custom design. The proposed HFCG has a reference clock of 100MHz and output a clock with the high frequency of 1GHz. With the comparison of the equivalent design, the proposed HFCG has lower power consumption, faster lock-in time and a smaller die area.