Design Of A Low Jitter Delay Locked Loop Circuit For TDC

As the key component of the integrated circuit, the clock genneration circuit has a great influence on the performance of the system. The clock signal quality decides the performance of the circuit system, especially for measurement and conversion circuits, such as Time to Digital Converter. Delay Lock Loop has the negative feedback loop inside the system and can provide stable frequency clock. Changes of process, temperature and other conditions have a less influence on the clock frequency for voltage-controlled delay line. Because of these unique advantages, delay locked loop has more extensive application in the clock fields.In this thesis, considering the requirements of high quality clock for TDC, a low jitter DLL system architecture is proposed. This paper analyzes the noise transfer character of DLL according to its system transfer function. And then the design method for low noise DLL system is concluded. In system architecture, start controlled circuit is used to prevent the false lock and harmonic lock problem of DLL. System loop bandwidth and parameters of each module are calculated according to the low noise design theory. The charge pump adopts wide swing cascode structure and internal feedback loop to achieve a better match between the charge and discharge currents, and inhibit charge-sharing and other non-ideal effects. In the phase detector, optimum design of reset path is proposed to reduce the output pulse width. VCDL is composed by differential delay cell to suppress the common mode noise of the input clock and has good linearity. In layout design, good layout planning, matching design of transmission path, isolation design of mixed and sensitive circuits, shielding design of high-frequency signal lines are adopted to reduce the parasitic interference and crosstalk between modules.Based on TSMC 0.35?m CMOS process, the DLL is simulated and layout-drawn by Cadence, and tapeouts in this thesis. The test results show that, in 3.3V supply voltage, DLL can respectively lock in 60MHz-240MHz, static phase error is 235ps@125MHz. Compared with the input clock, the error is less than 5% at different frequency; RMS jitter is up to about 3.6ps@125MHz, pk-pk jitter is up to about 35.07ps@125MHz. The DLL has the locked function and good performance.