Research On The Lock Algorithm Of Digital Delay-Locked Loop

For the requirements of clock distribution on modern microprocessors and system on chip, this thesis has summarized the implement types of the digital delay locked loop, focused on the research of digital successive approximation register-controlled delay locked loop according to the balance of lock-in speed, active area and power consumption. On the basis of the variable successive approximation register-controlled delay locked loop(VSAR DLL), the shift-variable successive approximation register controlled delay locked loop(S-VSAR DLL) is proposed.The main work of this thesis is as follows:1, this design adds shift-controller in the logic controller of VSAR DLL. Running the double search algorithm before the the binary search algorithm, so the harmonic lock in the traditional SAR DLL is avoided.2, this design realizes the binary search of the response controlled word SAR after the shift-controller finished the double search.3, this design adds the free-false lock controller to avoid the disadvantage of locking once time of traditional SAR DLL. After the DLL enters into the false lock state from the lock state due to the environmental factors, the DLL restarts the locking process again, then achieves the phase lock state again.By the front-end design and simulation of S-VSAR DLL, the result has proved the correctness of the improved ideas. When the effective control word is 3, the longest lock time of S-VSAR algorithm reduces 11.1% compared with the VSAR algorithm. When the effective control word is 12, the longest lock time of S-VSAR algorithm reduces 75.9% compared with the VSAR algorithm.