Research And Design Of A Programmable Digital Delay Locked Loop

Delay lock ring(DLL)is a kind of clock generation circuit.Compared to the Phase Locked Loop(PLL),it has the advantages of simple structure,no accumulated phase error,stabilized loop,high noise sensitivity,low output jitter noise,and also has the characteristics that the stability and operation performance is not affected by temperature,power supply voltage and the manufacturing process.Therefore,DLL has been widely used in the areas of phase synchronization,clock skew,multiphase clocks acquisition,and so on.And it has become an indispensable part of today's very large scale integration circuit(VLSI).In recent years,with the development of integrated circuit technology,users' demands for power consumption,on-chip clock frequency,locking time,anti-interference and other aspects have gradually increased,which makes the research and development of high-performance programmable DLL circuit with wide working frequency range,low jitter and low power consumption become one of the research focuses in the field of VLSI design.On the basis of summarizing other designs,this paper intends to solve the deficiencies of the existing DLL structure,broaden its working frequency range and improve the anti-interference ability of the system,so as to meet the application requirements of high-performance DLLs.As the background of the research of a domestic field programmable gate array(FPGA),and based on the GF 28 nm standard CMOS process,a high-performance programmable DLL circuit structure with wide operating frequency range and low power consumption is proposed with a fully customized design method.The specific contents of this paper are as follows:Firstly,the research status and development trend of DLLs are described.The working principle and performance parameters of DLLS are analyzed and discussed.By studying the principles of three categories of existing DLLs in depth,the advantages and disadvantages of the existing DLLs are compared from the perspective of circuit structure and application scope.Secondly,according to the system requirements,the design index is proposed,and the DLL system architecture is built.By adding digital phase shifter,the whole circuit performance is improved.The functions of reset,phase shift,stationary phase shift and clock skew removal are analyzed and studied in detail.Thirdly,based on the analysis of DLL circuit functions and design index,the design process of each functional module circuit is elaborated in detail,and the circuit pre-simulation is completed to verify its functional correctness.Finally,the layout design and post simulation of the proposed programmable digital DLL structure are carried out.And the results of the pre-simulation and the post-simulation are analyzed and compared.The simulation results show that the delay accuracy is 92 ps at the standard power supply voltage of 1.0V.The manageable clock signal frequency range is 19MHz~500MHz,the total power consumption of the system is only 15.42 mW,the overall layout area is 432?m × 144?m,and its performance index fully meets the system requirements of the FPGA chip.The research innovations of this paper are as follows:(1)By analyzing the principle,advantages and disadvantages of several existing delay elements,a fully differential delay element with cross-coupled load is proposed.The propsed sturecture improves anti-interference ability of the delay line to the environment noise from power supply and substrate coupling noise.At the same time,it guarantees to obtain larger output swing and steeper signal edge.By using differential clock,the output clock jitter and duty ratio distortion are reduced.Thereby,compared with single ended signal,the power consumption is lower,and the working speed is faster.(2)Aiming at improving the flexibility of the DLL system's output clock,a configurable full difference integer and half integer frequency divider with equal duty cycle is proposed for high-speed DLLs.Based on the idea of periodic insertion,a differential interlocking circuit is designed by means of periodic insertion of differential clock signal and pulse broadening.Compared with the traditional frequency divider,this design has the advantages of high working frequency,good anti-interference and equal duty ratio.