The Reserch And Implementation Of Delay Line Locked Loop In The Frequency Synthesizer

With the rapid development of electronic technology,The system requirements forthe frequency source are more and more strict, A high-quality frequency source includeLow phase noise, high resolution, wide bandwidth, low frequency hopping, easyintegration and high stability. High purity source has become a hot topic of researchtoday.This design is mainly divided into two parts: Phase-locked loop(PLL) and delayline frequency-locked loop(FLL). In which the phase-locked loop commonly usedfractional frequency of so that frequency resolution of1Hz, Larger problem for thefractional-N spurious modulation and charge pump the DAC gain compensationto be improved.This paper first introduces a delay line frequency-locked technology toimprove the phase noise theory and derivation, On this basis, then gives the overalldesign the delay line locked phase-locked loop, and subdivided into fractional-N PLLdesign and delay line frequency-locked loop design. based on program is primarilydesigned two loops of the hardware part of the circuit,among Phase-locked loop circuitintroduce a substantial part: Such as the phase detector circuit, the charge pump circuit,the variable loop filter circuit, a frequency dividing circuit, and a VCO circuit design.Delay line frequency-locked loop introduces its voltage-controlled phase shifter andmixer phase detector part. After the completion of specific two Leveled VCO simulationdesign process. Finally, on the design of the circuit test results meet the designrequirements.The frequency source In this paper, the design of Final delay line frequencydiscriminator technology to achieve a phase-locked loop phase noise improvement.Specific indicators of the phase-locked loop design is: Frequency range(500MHz-1GHz), phase noise (≤-100dBc/Hz@20kHz), frequency resolution (1Hz),the output power (+10dBm), Access delay line frequency-locked loop phase noiseimprovement of about10dB. Not fully take into account the rapid transition whensampling learning circuit design, the last rapid transition frequency offset, signal greatercompensation to correct the frequency offset. Finally, because of time, frequency-locked PLL voltage-controlled oscillator commercialization to ensure that issues can besuccessfully completed, the frequency of late as long as the design of the VCOinvestment board debugging, it can be successfully applied to the design source.