On-chip Capacitance PLL Frequency Synthesizer With Loop Stability Compensation Based On Voltage Control Delay Line

With the development of modern electronic information technology and wireless communication,the demand for clock signals has increased.The phase-locked loop frequency synthesizer with good stability,high integration and wide frequency range is widely used in signal generation.Under low input reference frequency,the loop bandwidth limits the integration of the phase-locked loop system,because the loop-filtering circuit of the conventional phase-locked loop requires a large resistor-capacitor.It is the motivation of this paper that reduces the on-chip filter capacitor and the chip area to integrate the phase-locked loop with low input reference frequency at low cost.In this thesis,an innovative phase-locked loop compensation technique that based on voltage-controlled delay line is proposed.With a small chip area and low power consumption,a zero is generated for loop stability compensation.This zero replaces the zero,1/R₀C₀,generated by the second-order filter in the conventional structure,so that the resistance R₀and the capacitance C₀can be significantly reduced.The loop stability can still be achieved and the bandwidth remains unchanged.The compensation principle of the proposed structure is analyzed,based on the small signal linearization analysis method.The theoretical analysis is verified by MATLAB simulations.The thesis also analyzes the influence of the noise introduced by the delay line module on the output phase noise.The analysis shows that the noise introduced by the voltage controlled delay line module is suppressed due to the low-pass characteristic of the loop,which has little effect on phase noise.Finally,a prototype is designed to verify the effectiveness of the proposed structure.The prototype's input reference clock is 32k Hz and output frequency tuning range is from64MHz to 128MHz.The thesis elaborates the design process and gives the specific design of each module circuit.Based on 0.18?m CMOS process,the phase-locked loop is simulated by MATLAB and cadence spectre.The simulation results show that the phase noise is-103d Bc/Hz at 500k Hz,the stable locking time is within 1.3ms,the power consumption is less than 300?A@2.4V,and the prototype area is less than 0.1mm².