Based On Of Cfcs The Mdac Research And Design

The increasing demand for low-power high-speed and high-resolution ADC ICs becomes obvious, resulting from rising applications in wireless communication, video process and countless of digital devices. In this dissertation, a in-depth and detail research for the key module MDAC built-in 12-bit 100MSPS pipelinede ADC has been done. A new CFCS (Commutated Feedback-Capacitor Switching) technique is introduced into this module to improve systemic performance.Firstly, a detailed analysis of dominant error mechanisms introduced into the system by MDAC is provided. Given a full consideration of the performance, stage resolution is distributed to every stage. In order to reduce power dissipation further, as a useful method scaling down technique is adopted to optimize systemic structure.Secondly, a complete theory analysis of CFCS technique is finished, and a reasonable MDAC systemic structure is presented. Compared with traditional technique, CFCS relaxes the capacitor matching resquirement and gets higher linearity. To realize this technique in circuit, traditional capacitor array has been modifies and a new encoder has been conceived in the MDAC.Thirdly, during the process of circuit designing, a two-stage amplifier is proposed as the main amplifier in MDAC, which has high gain and high output swing. Pole-zero canceling with a resistor is adopted to get wide GBW and appropriate PM. continuous-time and switch-capacitor common-mode feedback are designed, and used to the output of two stages respectively.Lastly, the MDAC has been simulated by Cadence EDA software with standard SMIC 0.35um/3.3V Si-CMOS process model. The results show that every MDAC satisfies the requirement of ADC system at 100MHz sampling frequency. Taking the first stage MDAC as example, its main amplifier DC gain is 89.2dB, GBW is 2.21GHz, PM is 26°. During time domain simulation, its settling time is 4.47ns, settling resolution is 499.4mV, slew rate is 586V/μs.Therefore, this MDAC can reduce capacitor mismatching error by CFCS and fullfill the requirement of 12-bit 100MSPS pipelined ADC.