Design Of 16-bit 120MSPS Pipelined ADC

The vast majority of signals in the real world are analog signals that change continuously with time.On the other hand,with the rapid development of digital integrated circuits,digital signals greatly improve the ability of human to process data.The analog-to-digital converter(ADC)mainly converts analog signals in the real world into digital signals that can be processed quickly by the system,so its importance is self-evident.ADC has always been a key module of communication system,especially in the fifth generation mobile communication(5G),which requires ADC to have higher accuracy,faster speed and lower power consumption.Pipeline ADC is always the preferred structure in high-precision,highspeed communication system because it can achieve accuracy,speed and power consumption at the same time by allocating sublevel accuracy reasonably.This paper will focus on the high-precision,high-speed,low-power pipeline ADC system architecture and its key circuit design.Based on the CMOS 0.18?m process,this paper designs a 16-bit 120 MSPS switch capacitor structure pipeline ADC,focusing on the 3.5-bit,1.5-bit pipeline sub-stage and overflow calibration technology in the pipeline ADC.First determine the pipeline ADC system architecture as "3.5+3.5+1.5+1.5+1.5+1.5+1.5+1.5+1.5+3" to take into account speed and power consumption;use MATLAB tools to conduct behavioral-level modeling of the ADC structure to verify the architecture effectiveness.In terms of circuit design,the pipeline substage is mainly composed of MDAC and Sub-ADC.In the MDAC architecture,the MDAC in the first two 3.5-bit sub-stages uses a charge redistribution architecture with overflow detection function,and the MDAC in the 1.5-bit sub-stage uses a traditional capacitor fliptype architecture;the residual amplifier in the MDAC uses a telescope-type gain The twostage amplifier of the improved stage has gains of 96 d B and 88 d B respectively;the voltage comparator in the Sub-ADC adopts a switched capacitor type comparator composed of a pre-amplifier and a latch,and its offset voltage is 1.93 m V;at the same time,it is suppression for the quantization error caused by the "bubble" code,the decoder in the 3.5-bit sub-stage adopts the Gray code as the decoding method of the intermediate code.Finally,a brand-new overflow bit detection method is proposed.The most significant bit(MSB)of the first two3.5-bit sub-stages output digital codes is the overflow judgment bit,and the judgment of the overflow condition can be realized through a simple logic circuit.After the module circuit design is completed,the functions and performance of each sub-module circuit are simulated and verified.The simulation shows that under a sinusoidal signal with an input frequency of 10.0098 MHZ and a differential swing of 2.4V,the effective digits of the output of the first three pipeline sub-stages are 13.7bit,12.25 bit,and 11.92 bit,which all meet the accuracy of the subsequent sub-stages to the previous stage.When the input signal frequency is 12.1918 MHZ and the sampling frequency is 120MS/s,the ADC's SFDR is 92.4d B,SNR is 95.5d B,SNDR is90.7d B,and ENOB is 14.77 bit,which meets the design index requirements.