High-speed Parallel A / D Conversion Design

High-speed parallel CMOS ADCs have been widely applied in many applications, such as communication systems, disk I/O, medical image apparatus, HDTV, etc. As the interface of Digital system and Analog Systems, ADCs are indispensable in these applications. With the development of SoC design, the embedded ADC becomes one of the most important IP cores. Requested by communication/video system, many studies focused on high-speed, middle/low resolution, embedded ADCs which generally have problems such as digital CMOS process incompatibility, high power dissipation, large area, noise disturbance. This research analyzes these problems theoretically, and proposes some novel circuits, such as master-slave T/H circuit, low power comparator, dynamic encoder, etc. In the design of high-speed parallel ADC, a trade-off design is proposed that account for power dissipation, speed and accuracy. This project also studied and summarized the applications of the current-mode circuit in ADCs. They are listed as follows:1. A master-slave T/H circuit with offset compensative amplifiers is proposed which can improve sample precision and input bandwidth. This circuit can meet the sampling requirement of high-speed middle/low resolution ADCs.2. In this thesis, the principle of regenerative current comparator is quantitatively analyzed. Based on this theoretical analysis, a novel high-speed current comparator with anti-noise latch is proposed, which can significantly reduce power dissipation and suppress the noise disturbance of digital circuit.3. The speed, power dissipation and accuracy of folding & interpolating ADC are analyzed, and an optimum design method of ADCs is proposed according to the folding ratios, interpolating ratios, the number of folders.4. A dynamic encoder is proposed based on domino circuit to convert temperature codes and cycle temperature codes into binary codes. With the compressed codes, this dynamic encoder can be applied to 4-10bits parallel CMOS ADCs. It has several advantages: high speed, small area and low power dissipation.5. All the main circuits and the 6-bit Fine ADC circuit have been simulated in 0.6um BSIM3v3.2 BiCMOS process by HSPICE.The layout of them have been drawn by tanner using the design rule of 0.6μmBiCMOS and pass the DRC verification.