Configurable 32bit Fixed-point FFT Processor Chip Design

FFT has become the core technology of digital signal processing technology, and it has been widely used in many fields.As a kind of fast transform algorithm, FFT algorithm makesthe applications of DFT algorithm in engineering to become a reality. Especially in the field of communication, 4G and other popular communication technologiesare based on the OFDM system, therefore, to design a high performance FFT processor appears to be particularly important.This paper mainly studied the realization of FFT processor ASIC design.Firstly, common FFT algorithms are described in Chapter Two.Based on the comparison of Radix-2, Radix-4, Radix-8 and Radix-23 algorithms,mixed Radix-2 and Radix-23 algorithm is selected in my design.In the aspect of circuit design, the structure of Radix-23 butterflyunit is improved, so that it can be configured to achieve all the Radix-2, Radix-4 and Radix-8 algorithms.The complex multiplier is simplified, and one real multiplier is reduced.Through the design of the conjugate module, the hardware multiplexing of FFT and IFFT option is realized. Finally, using the Simulink model to verify the system and each module,ensures the feasibility of the algorithm and circuit.This paper completed the FFT processor RTL design and simulation.Finished FPGA verification based on Altera DE3 development board.Completed DC synthesis and formal verification.Completed designing the layout of FFT processorwith SMIC 0.13?m process.The total area of the layout is 1.54*1.57 mm2.The package of the chip is QFP64 with 64 pins,and the size of the package is 7mm*7mm.At present, has completed the test of the chip.When the frequency of the FFT core clock is 60 MHz, for a 64-point FFT operation, processing delay time is 5.33?s in continuous mode,and it costs 3.2?s finishing 64-point FFT operation.The power consumption of the core is 39 mW.