Can Be Extended Plural Symbol The Number Of Fft Research And Asic Implementation

With the development of digital electronic technology, digital signal processing technology has already been widely applied in communication, voice processing, computer, multimedia and other fields. As one of the core technologies of digital signal processing (DSP), Fast Fourier Transform (FFT) makes the running time of Discrete Fourier Transform (DFT) shorten several orders of magnitude.This thesis discusses a scalable structure of FFT implemented in the ASIC, which adopts reusing modules and butterfly multipliers. A modified version of booth encoding and wallace tree structure are used in the multipliers to calculate the result. Based on 8-point FFT this design can be expanded to 16-point or 32-point structure, also can be switched to other modes at any time according to mentioned three modes. After the design is discribed in verilog HDL ,it is implemented and verified by integration into a chip.The main work of this thesis is as follows:1. Based on the analysis of three kinds of Fast Fourier Transform(FFT) algorithm, radix-2 decimation in time (DIT) is chose to carry out scalable FFT.2. The whole circuit of the FFT processor is designed and described in Verilog HDL according to the widespread ASIC design flow: RTL coding, functional simulation, logic synthesis, layout and routing, verification, parasitic extraction and post-simulation. And the post simulation results show that the circuit meets the design requirements.3. A specialized scalable complex FFT is designed with the 0.18μm CMOS process, and the chip is taped out using MPW (Multi Project Wafer) on SMIC process line. The chip size is 2.800 mm×2.350mm, and the circuit scale is about 2 million gates.4. After the test circuit was completed. the chip was tested under 10 MHz clock frequency, and the results show that the chip works steadily.