Design And Research Of FFT Processor Based On Improved CORDIC Algorithm

This paper designs a FFT processor based on CORDIC algorithm,which’s architecture isiterative based on storage. The complex multiplication in FFT computation is implemented byCORDIC algorithm.The butterfly unit is DIF-4, which is implemented by a four statesmachine, which controls and schedules the complex adders and complex subtracter, thismethod of hardware reusing reduces of the hardware resource.According to the different quadrants of rotation angle, the direction of rotation isdifferent, sometimes is counterclockwise and sometimes is clockwise.Therefore, the rotationunit uses a adder-subtracter which consumes much hardware. This paper improved theCORDIC algorithm, according to the different quadrant of rotation angle exchanges the x, ydata ahead of time, which lead to direction of rotation unit is always a single direction, so therotate unit just uses an adder and a subtracter,consuming a little hardware.This paper designs a1024-points FFT processor based on improved CORDIC algorithm,The format of the input data is fixed-point. we also write the testbench for circuit simulation,the modelsim simulation shows that the circuit function and the the timing are correct. Theoutput data of modelsim simulation is the same as the Matlab’s, further verified by the FPGA.At last, we synthesizes the circuit in Altera cycloneII EP2C5F256C6devices without anyconstraint, the FFT circuits consumes2857LE and the maximum operating frequency is99.48MHz. we also systhesises the circuit with technology library of semiconductormanufacturing international corporation (SMIC) in180ns process, the maximum operatingfrequency if149MHz, the area is1.502mm~2, dynamic power consumption is34.77mw andleakage power consumption is18.8μw.