The On-chip 10-bit 40 Mhz Pipelined A / D Converter Design

With the rapid development of semiconductor technology, integrated circuit has stepped into a new era of SoC. High-speed, low-power A/D converters are widely used as analog IP, especially in SoC for communication and video processing. Compared to other architectures, the pipelined architecture ADC is creditable for high speed and high resolution. In this paper, a 10 bit 40Msample/s is designed using SMIC 0.18um CMOS mixed-signal process.Considering the tradeoff among high-speed, low-power, small die area, and low-voltage supply, the whole ADC is comprised of 9 stages, 1.5 bit per-stage, and some power optimization techniques on the architecture level are adopted, such as the choice of stage resolution, capacitor scaling and digital correction. In addition, the design of Sample and Hold circuit (S/H Circuit) is the key to realized the pipelined ADC. The operational -amplification (OP-amp)'s constraints of gain and bandwidth can be deduced by analyzing the error of the ADC.The circuit is simulated by the Spectre simulator which is based on SMIC PDK of 0.18um CMOS model. The post-simulation results reveal that the ADC designed with this method achieves the 9bit ENOB at full speed of 40MHz when input frequency is 9MHz. The die area is 1200um*1200um, and consumes 70mW from a 1.8-V supply.