For High-speed High-precision Pipelined Adc Sub-ad Cell Circuit Design

Recently, the development of analog-to-digital converter (ADC) is greatly increased by the demand of mobile consumer electronic appliances. The consumer market requires more and more A/D converters. In this thesis, a 12-bit 100MSPS pipelined ADC has been analyzed. Then novel circuit topology are explored and investigated for sub ADC. The main results are as follows:Based on the analysis of high speed, high resolution pipelined ADC, and system overall specification, the requirements of sub ADC specifications are discussed. In addition, different error sources in sub ADC are analyzed.A novel topology of switched-capacitor preamplifier latch (SCPL) comparator is proposed. The delay time and power dissipation of the comparator is optimized. Based on modeling analysis of switched-capacitor network, the negative influence of charge injection and clock feedback on system resolution is decreased largely. Delay time is decreased using one stage amplifier with source follower as pre-amplifier of comparator. According to load ability of reference buffer, the resistor network is optimized. Clock controlled encode circuits is designed for 3.5bit/stage, 1.5bit/stage and the last 2bit flash ADC. To decrease system power dissipation, the dynamic comparator is used in the middle 7 stages of pipelined ADC.With standard 1.8V/0.18μm Si CMOS process model, the circuits of sub ADC have been simulated by Cadence EDA software. The simulation results indicated that, the delay time of SCPL comparator is 556ps, the power dissipation is 188.6μW, the resolution is 0.23mV, and settling time is less than 1.2ns. When used in 3.5bit/stage sub ADC, the SCPL comparator can work smoothly at 100MHz clock. When the optimum value of ladder resistor is 1.5KΩ, in 3.5bit/stage, the glitches introduced to reference voltage is 0.24mV. Sub ADC simulation results shows that the total power dissipation is 9.566mW. The sub ADC power is decreased by 15.1% when compared to traditional sub ADC structure. It is indicated that the designed sub ADC circuits can be used in the 12bit 100MSPS pipelined ADC system. The whole system can operate in lower power dissipation and satisfy system performance.Using 0.18μm 1P6M mixed-signal model, with the integral floor plan, circuits cell separation, and geometry matching design considerations, layout of different sub ADC stages are designed, with Cadence software tool.