Design Of An On-chip 10-bit 20-Msample/s 49mW Pipelined A/D Converter

In a mixed signal system, the ADC (Analog-to-Digital Converter) is always an indispensable component. Compared to other architectures, the pipelined architecture ADC is creditable for its high speed and high resolution. Generally speaking, it's reasonable to adopt the pipelined architecture for the ADCs whose resolution is 10-bit or more and sampling rate is above 1MS/s.This thesis focuses on the research of a high performance and low power Pipelined A/D Converter which is fabricated in a 0.6pm double-poly double-metal CMOS process. The digital correction technique is used to relax the offset requirement of the comparators. To reduce signal-dependent charge injection and substrate noise injection, the bottom-plate sampling technology is applied. A sample-and-hold amplifier (S/H Circuit) is also used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. The circuit is simulated by the Hspice software which is based on CSMC's library of 0.6μm mixed-signal CMOS model. The simulation results reveal that the ADC designed with this method achieves the SNDR of 58dB at full speed of 20MHz when input frequency is 4.125MHz. Furthermore, the ADC consumes 49mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators.