Research And Design Of A 10bits 40MSPS Pipelined ADC

System-on-chip (SOC) requires the integration of analog circuits and digital circuits on a single chip. Technology compliable, performance optimized analog-to-digital converter (ADC) is an important building block in SOC. It has been an important research topic to improve the performances of ADCs such as speed, resolution, power dissipation, easy-to-integration by adopting standard CMOS technologies and improving available architectures.It's researched and designed a low power pipeline architecture CMOS analog-to-digital converter with operational amplifier (op-amp)sharing technique in this design. The main blocks of the pipeline ADC are as follows: Sample and Hold circuit, Multiplying DAC, sub-ADC, clocking generator and the digital correction circuit. Considering the speed , power dissipation and specifications, A flip-around sample and hold circuit was designed to reduce the power consumption; S/H circuit is followed by eight 1.5-bit stages and a final 2-bit flash sub-ADC. A digital correction circuit is used to eliminate errors between stages; In order to reduce the power consumption of the ADC, operation amplifier sharing technique and scaling down technique was used. In sample and hold circuit and Multiplying DAC, a gain-boosting op amp was used to insure the speed and precision of the Switch-capacitor circuit. A latch comparator with pre-amp has been used to reduce the kick-back effect.The EDA tools used in this project are Cadence .The design has been implemented with a single power supply of 2.5V for a single poly five metal TSMC standard CMOS 0.25um process. The results show that the input of ADC range from 0.75V to 1.75V, Its resolution is 10 bits and sample rate is 40MHz, power consumption is about 80 mw and the parameters of the whole circuit meet the design requirements.