Research And Design Of A 10bits 80MSPS Pipelined ADC

With the great development of wireless communication, analog-to-digital technique, which is one of the key techniques in wireless communication, is being made amazing progress due to the more and more demand from products. Pipelined ADCs, one of the most popular ADCs, are mainly used in those fields which look after both resolution and speed, such as wireless LAN in communication, cell phone and high-resolution digital TV in custom electronic products.It's researched and designed a 10-bit 2.5V 80MSPS Pipelined CMOS ADC(analog-to-digital converter) in this design: Given a full consideration of the speed, power, area and dynamic performance, the 8-stage, 1.5bit/stage and 2-bit flash ADC last stage structure is introduced. And digital correction circuits are added to diminish errors between stages. The whole circuit consists of the sample-and-hold circuit, the sub-ADC, the sub-DAC, the clock generator, the time synchronizer and the digital calibration circuit. Finally, the layout of some typical blocks of this chip is designed with the Virtuoso.The simulate tool used in this project is Spectre of Cadence, based on the TSMC 0.18μm CMOS process library and under the Linux OP. The results show that the input of ADC range from 0.65V to 1.85V, its resolution is 10 bits and sample rate is 80MHz, power consumption is about 160 mw and the parameters meet the design requirements.