Design And Implementation Of Delay Management Module Applied To FPGA Chip

With the development of integrated circuit technology, the performance of theFPGA chip has been increasing, which is widely used in the communications field, computing field and consumer electronics. Higher requirements on flexibility and compatibility of the FPGA chips are put forward. To support more kinds of transmission protocol, more and more commercial FPGA chips offer the delay management circuit in their IO cell, which is designed for precise delay adjustment and control. This allows the FPGA chips to be compatible with a variety of transmission timing requirements, and also improve the reliability of data transmission effectively.Using traditional delay chain to adjust the delay time of the data path is feasible, but the delay cell is very susceptible to the influence of PVT change, leading to varies of delay length. That will not only restrict the speed of data transmission, but also deteriorate the reliability of the transmission.It is in such context, this paper presents a novel Delay Management Circuit using a digital controled delay-locked loop as calibrater of the delay chain. As well as the DDLL circuit is locked, the delay length of the delay chain is only determined by the period of the reference clock, neither the chip process nor the working environment, thus providing a constant delay adjustment resolution.Optimized for the digital CMOS process, the proposed delay locked loop for delay calibration is designed into digital architecture. Taking full advantage of the characteristics of the DDLL and available clock resources, the innovative idea of oversampling quantification is proposed, which avoids using a complex traditional TDC circuit, while providing good accuracy. A1bit TDC is used for quantization of the phase error, and the complexity of the circuit is simplified.The proposed delay management circuit is fabricated with65nm digital CMOS process. Achieving a78ps adjustable delay resolution, during a5ns adjustable time range. The lock time of DDLL is less than600ns, much better than theVirtex-4family (for which3us is necessary) to achieve the same resolution.