The Research And Design Of Delay Locked Loop Based On High-powered FPGA

With the very large-scale integration circuit developing fleetly,the integration of digital system becomes more and more integrated,meanwhile operates more and more rapidly. In high-density FPGA design, the quality of clock-distribution on chip becomes more and more magnitude. The clock delay and skew have been the key factors which affect system performance deeply. Delay phase-Locked Loop being an important component of clock network in FPGA design can reduce the skew of clock, meanwhile supply lock-in clock synchronization and a series of functions for system so as to suffice all kinds of timing in FPGA design.In order to eliminate the clock delay effectively in FPGA, meanwhile minish the skew of clock, this paper researches and then designs total digital DLL dedicated on FPGA. During the process of designing digital DLL, first of all, this paper put forward the frame of the whole circuit, then analyzed and researched the principles and implementations of all basic modules. Total digital structure makes DLL steadily and unconditionally, and won't cumulate phase error. Allowing for low power consumption, LDO technique was imported in this circuit. In this way, the circuit will not only reduce the power of the delay module in DLL, but also economize the logic resource requirements in a certain extent.This total digital DLL circuit this paper researched in is one certain part of FPGA chip with 300,000 gates implemented in 0.22μm CMOS standard technics. As simulation verified, in normal operating status this digital DLL allows the input range of clock is from 50MHz to 200MHz, the DLL can eliminate the clock transferring delay and implement clock synchronization, meanwhile provide multi-frequency clock,various sub-frequency clock and clock phase shifting.