Active Analog Delay And Delay Locked Loop

With the development of high-speed mixed-signal circuits,signal timing for the overall system have a crucial impact.Therefore,circuit design often need to add a number of delay elements,to compensate for delay differences between the path to achieve specific performance requirements.The delay circuits are widely used and can be used in wideband beamforming system circuits,finite impulse response(FIR)filters,infinite impulse response(IIR)filters,and equalizer.So,the research and design of high-performance delay circuit has important value and significance.In this paper,active delay circuits and a delay locked loop are designed using IBM 0.13?m SiGe BiCMOS process.This paper introduces the active delay circuit of gm-C structure based on the basic principle of delay circuit and the comparison of various delay circuit structures.Delay circuit uses high performance SiGe HBT as input transistors to improve the frequency range of delay circuits.Variable capacitor is used to adjust the circuit delay time.Delay circuit also uses inductive peaking and emitter negative feedback technology to expand the circuit bandwidth.In order to reduce the reflection of the signal in the input and output ports,designing matching circuits to guarantee the reflection coefficient of the delay circuit is less than-10dB in the operating frequency.The delay locked loop in this paper can adjust the delay time of the delay circuit,so that the delay time in different process angle,temperature and voltage is constant.The delay locked loop consists of delay circuits,a multiplier,and a V/I converter.The delay locked loop has a negative feedback adjustment function,which ensures that the total delay of the delay circuit in the loop is one quarter of the clock cycle.In order to reduce the phase error introduced by each module in the loop,a fully symmetrical four-quadrant multiplier and a low offset V/I converter are designed,which can effectively improve the locking accuracy of the delay locked loop.The whole chip size is 500?mx800?m.The test results show that the average delay time of the single stage delay circuit can be kept within 8ps in the range of 4-12GHz.When the control voltage changes,the single-stage delay circuit delay time can change from 7.3ps to 8.4ps.The matching circuit can ensure that reflection coefficient S11 and S22 of the circuit is less than-10dB in the bandwidth of 0.2-25GHz.When changing the frequency of clock signal,the delay control loop generates the control voltage to adjust the delay time of the delay circuit and increases the stability of the delay circuit delay.The design of the delay circuit and the delay locked loop has some significance in the research of the low delay wide band delay circuit in the future.