Design Of Clock Network Based On DLL In FPGA

As a main part of the clock distribution network in the FPGA, the phase-locked circuit plays an important role in the performance of the whole chip and system, especially in the high speed application fields.In this thesis the basic architecture and the performance evaluation of phase-locked loop are presented. Based on digital delay-locked loop, the mix signal technique is used to implement the digital delay locked loop with the resource control technique. During the design of delay- locked loop, the frame of the whole circuit is introduced and then the principles and implementation of the basic modules are presented. Based on the consideration of reducing power consumption, the shut-down power supply control technique is used. It consumes less power in the low voltage state when DLL works. However the power supply of the DLL will be shut down while it does not work, so this approach reduces the power consumption greatly.The DLL designed in the thesis as a part of the FPGA chip, achieves the clock distribution with high performance, which is fabricated in 0.25um CMOS normal process. In this digital DLL the input clock can be adjusted between 25MHz and 200MHz. Compared with the counterpart designs, the proposed digital DLL has the advantages of high precision and low power consumption with high performances.