Research And Design Of FPGA Delay Locked Loop Architecture

FPGA(Field Programmable Gate Array)chip is an important part of IC industry products. More and more IC designs and simulations are implemented using FPGA. Today's FPGA chip market is dominated by US or Europe companies and almost no FPGA series product is designed and manufactured in China, which makes this paper significant valuable according to this research direction. Based on a SRAM FPGA chip project that is fabricated using the SMIC 0.25um CMOS process, research and design of FPGA inside-chip Delay Locked Loop (DLL) architecture is presented and a new fast-lock version DLL architecture, OSDLL, which can balance lock time cost and stable clock management performance, is introduced and designed.The DLL designed in the thesis is a part of the FPGA chip project. In this paper the principles and implementation of the basic modules are presented and the frame of the whole circuit is introduced, in which digital control logic is designed through half custom flow and other sub-modules such as phase detector, programmable delay chain and clock generator are designed according to full custom design flow. After digital & analog mix-simulation of DLL, the whole design is embedded in FPGA chip circuit and this FPGA is fabricated using the SMIC 0.25um CMOS process. The test result of FPGA MPW shows that DLL runs well both in function and performance perspectives. The input frequency range of the FPGA DLL designed in the thesis can be operated from 20MHz-200MHz. Compared with the counterpart designs, the proposed DLL has the advantages of high precision and low power consumption with high performances.Based on the formal version DLL,a new Fast-lock Delay-Locked Loop, OSDLL, is designed. OSDLL can lock much faster than DLL while it still maintains stable clock management ability. One-shot delay calculation technology is used in OSDLL and works smoothly together with DLL adjusting mechanism. OSDLL doesn't cost much more silicon space and raises lock speed tremendously which brings the performance of DLL and user design to another level.DLL module can be used widely in IC design field as embedded clock management circuit in ASIC or FPGA and build-in IP in SOC. In FPGA chip DLL can synchronize clock, act as a clock doubler or divide the user source clock and also provide high quality clock source to board level to simplify design.