Key Technology Research Of Low-voltage And Low-power ?-? Modulators

As a significant interface block in electronic systems,the analog-to-digital converters(ADCs)are widely used in various kinds of electronic equipments.With continuous progress of semiconductor manufacturing and design technology of integrated circuits,the low-voltage,low-power ADCs are becoming hot research issues in both academic and industrial fields under the collaborative design requirements of digital integrated circuits and in the application of biomedical,audio and energy-harvesting fields.Thus,it is very important and meaningful to research the?-?modulator,one of the main structures of low-voltage low-power ADCs.The author of this paper chooses the low-voltage,low-power?-?modulator as the research object,researching and discussing its working principle and low power design technology.The main contents and innovation points of this paper are shown below:(1)Behavior modeling of the CIFF(Cascade of Integrators Feedforward)3^rd order 1 bit?-?modulator.According to the performance requirements,the order of the modulator is set as 3 and the quantization bit is selected as 1.The modulator is designed with the CIFF structure which features low output signal swings to ensure the modulator could work properly in low voltage environment(0.9 V).Before circuit-level design,a systematic model of the modulator is built in MATLAB/Simulink environment,and behavior-level simulation is conducted.During the process of simulation,the clock jitter,noise of the integrator,non-idealities of the amplifier and comparator are analyzed and modeled,and their impacts on the modulator performance are researched.The simulation results show that,the signal to noise ratio(SNR)of the model is 89.0 d B,and the signal to noise&distortion ratio(SNDR)is 88.2 d B,which meets the design requirements,and left enough performance margin for the subsequent circuit level design work.(2)Circuit level design of the CIFF 3^rd order 1 bit?-?modulator.Based on the behavior model,the circuit-level design of the CIFF 3^rd order 1 bit?-?modulator is conducted in a CMOS 40nm technology under the supply of 0.9 V.The integrator in the first stage is improved so that it could receive the signal from input terminal of the modulator and feedback digital-to-analog converter(DAC)in different phases,which reduces the impacts on modulator performance caused by sampling capacitors'mismatches and switching noise in the sampling branches.Besides,the bootstrapped switches are used to improve the linearity of the sampled signal,and bottom plate sampling technique is adopted to avoid the influence caused by injected charges.In order to obtain a large output voltage swing,the operational amplifier is realized in a two-stage common source structure.The comparator is implemented in a simple two-stage dynamic structure to avoid extra power consumption since its non-idealities has little effect on the modulator performance.The post simulation results show that,the modulator achieves an SNR of 85.5 d B,an SNDR of 83.8 d B and a dynamic range(DR)of 85.1d B with a total power consumption of 1.25 m W.The proposed modulator achieves a middle-to-high figure-of-merit(FOM)compared with international high-level works.(3)Design of a 3^rd order 1 bit?-?modulator with an FIR filter embedded.In order to increase the FOM,the structure of the CIFF 3^rd order 1 bit?-?modulator is improved.The improved modulator is also implemented in a CMOS 40 nm technology under the supply of 0.9 V.In the feedback path,a 2-tap FIR filter is inserted to reduce the integrator output swings further in low voltage environment.The filter is realized in a digital way to avoid the impacts on the modulator caused by passive elements'mismatches.In addition,assistant circuits are added into the bootstrapped switches to reduce the influences on the linearity.To improve the transconductance efficiency,the two-stage amplifier is modified into an inverter-based one.However,the power saved by modifying the amplifier structure is very limited,therefore the amplifier is split into two same parts,and partly closed during the sampling phase so as to reduce the power consumption substantially.The structure of the two-stage dynamic comparator also gets improved to reduce the power and the impacts of kick-back noise.The chip measurement results show that,the SNR and SNDR of the improved modulator are 87.1 d B and 85.6 d B respectively,and the DR is 87.2 d B.The core power consumption is 0.84 m W.Compared with international high-level works,the improved modulator achieves the best FOM.(4)Design of an inverter-based 4^th order 1 bit?-?modulator.On the basis of the 3^rd order modulator,a CIFF 4^th order 1 bit modulator under the supply of 0.9 V is designed in a CMOS 40nm technology.What distinguishes the modulator from the two mentioned above is that the fully differential amplifiers are replaced by pseudo differential inverters.The compensation capacitors are inserted in the integrator to eliminate the input offset and reduce its sensitivity to the DC gain of the inverter.In order to reduce the impacts on the inverter caused by process-voltage-temperature(PVT)variation,an extra low dropout regulator(LDO)is added to adjust the supply and DC operation points of the inverter to keep its transconductance constant.The two-stage comparator is modified into a single-stage one to reduce the power consumption further.Accoring to the post simulation results,the SNR and SNDR of this modulator are 86.1 d B and 84.9 d B separately,and the DR is 86.3 d B.The core power consumption of the modulator is 0.93 m W.The modulator achieves a better FOM when compared with international high-level works.